Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a vertical transistor.
In a sub-60-nm DRAM fabrication process, the formation of vertical transistors is desirable to increase the degree of integration of transistors in cells, simplify the fabrication processes, and improve device characteristics. A vertical transistor includes an active pillar and a vertical gate surrounding the active pillar. Due to the vertical gate, a channel of the transistor is formed in a vertical direction.
In general, an active pillar has a structure of a neck pillar and a top pillar, and a gate surrounds the neck pillar. However, the neck pillar usually has a weak supporting force, so that the active pillar easily collapses in the following process.
In an attempt to address the above-discussed concerns of the neck pillar structure, an active pillar without the structure of the neck pillar, i.e. a neck-free active pillar, has been developed.
FIGS. 1A to 1D illustrate a conventional method for fabricating a semiconductor device including vertical transistors.
Referring to FIG. 1A, a substrate 11 is etched using a hard mask layer 13, in which a hard mask oxide layer 13A and a hard mask nitride layer 13B are stacked, as an etching barrier to form neck-free active pillars 12.
Buried bit lines (BBL) 14 are formed by implanting impurity ions into the substrate 11 between the active pillars 12.
A gate dielectric layer 15 is formed, and a gate conductive layer 16 is formed along the profile/surface of a resulting structure including the gate dielectric layer 15. The gate conductive layer 16 is etched so that spacers remain to surround sidewalls of the active pillars 12.
Referring to FIG. 1B, a first separation layer 17 is formed over a resulting structure, and trenches 18 are formed to separate the buried bit lines 14.
Referring to FIG. 1C, a second separation layer 19 is formed to fill the gaps, i.e., the trench 18, and the height of the second separation layer 19 is lowered through an etch-back process. Since a gate length is determined by the length of the second separation layer 19 removed by the etch-back process, it is desirable to etch the second separation layer 19 uniformly. Unless the second separation layer 19 is removed from the upper sidewalls of the active pillars 12, the gate conductive layer 16 formed on the upper portions of the active pillars 12 is not etched properly. Therefore, a subsequent cleaning process is performed to cleanly remove at least the second separation layer 19 formed on the upper sidewalls of the active pillars 12.
Referring to FIG. 1D, portions of the gate conductive layer 16 formed on the upper sidewalls of the active pillars 12 are removed to form vertical gates 16A.
Word lines 20 may be formed to connect the adjacent vertical gates 16A to each other.
As described above, the conventional method requires a process of removing portions of the gate conductive layer 16, which are formed on the upper sidewalls of the active pillars 12, in order to form the gate electrodes 16A.
However, since the height of the active pillars 12 is 2,000 Å or more, in accordance with the trend towards a high degree of integration, it is difficult to completely remove portions of the gate conductive layer 16 from the upper sidewalls of the active pillars 12. Thus, a tail shaped portion of the gate conductive layer 16, as indicated by reference symbol “A”, may remain.
Furthermore, the second separation layer 19 may be excessively lost during the cleaning process subsequent to the etch-back process.